Brand new implication of your own physical HW limits to your coding model is that one never directory dynamically across hardware records: a sign-up document is also fundamentally not be noted dynamically. Simply because the latest check in matter is fixed and another often has to unroll explicitly to obtain fixed sign in number or go compliment of thoughts. It is a constraint common to CUDA programmers: when claiming an exclusive drift a beneficial ; and you will next indexing having a working worth contributes to so-named regional memories utilize (i.age. roundtripping to help you memories).
Implication toward codegen ¶
Which introduces the consequences towards fixed compared to dynamic indexing talked about in past times: extractelement , insertelement and you may shufflevector into the letter-D vectors from inside the MLIR merely help fixed indicator. Active indices are only offered with the extremely small step 1-D vector yet not the brand new exterior (n-1)-D . To other instances, explicit load / locations are needed.
- Loops around vector values is indirect dealing with out of vector opinions, they want to operate on specific load / store businesses over letter-D vector designs.
- Once a keen n-D vector kind of is actually stacked for the a keen SSA value (that may or may not live-in n data, which have otherwise versus spilling, whenever ultimately paid down), it may be unrolled to reduced k-D vector versions and processes you to correspond to the brand new HW. Which level of MLIR codegen is comparable to register allotment and you may spilling that exist much after regarding the LLVM pipe.
- HW get service >1-D vectors that have intrinsics having indirect addressing in these vectors. These could be directed because of explicit vector_shed procedures out-of MLIR k-D vector systems and operations in order to LLVM 1-D vectors + intrinsics.
As an alternative, we argue that really decreasing so you can good linearized abstraction hides aside this new codegen intricacies connected with memory accesses by giving an incorrect impression off magical active indexing around the information. Instead i love to build those people most explicit into the MLIR and you may create codegen to explore tradeoffs. Some other HW will demand various other tradeoffs regarding the designs involved in actions step one., 2. and you may step 3.
Decisions generated in the MLIR peak gets ramifications at an excellent much later phase for the LLVM https://datingranking.net/escort-directory/shreveport/ (immediately following sign in allowance). We really do not envision to expose concerns connected with modeling off register allocation and spilling so you’re able to MLIR explicitly. Alternatively, for every target tend to establish a couple of “good” target surgery and you will letter-D vector designs, on the costs you to PatterRewriters in the MLIR height will be capable address. Instance will cost you at MLIR top is abstract and you will used having ranking, maybe not to have specific performance modeling. Subsequently such as will set you back would be read.
Implication toward Decreasing so you’re able to Accelerators ¶
To target accelerators that support higher dimensional vectors natively, we can start from either 1-D or n-D vectors in MLIR and use vector.cast to flatten the most minor dimensions to 1-D vector
It is the role of an Accelerator-specific vector dialect (see codegen flow in the figure above) to lower the vector.cast . Accelerator -> LLVM lowering would then consist of a bunch of Accelerator -> Accelerator rewrites to perform the casts composed with Accelerator -> LLVM conversions + intrinsics that operate on 1-D vector
Some of those rewrites may need extra handling, especially if a reduction is involved. For example, vector.cast %0: vector
However vector.cast %0: vector